On the 15th-17th November 2023, A-IQ Ready project was presented at the XXXVIII Conference on Design of Circuits and Integrated Systems – DCIS 2023. This conference is a well-established international meeting that provides opportunities to both researchers in the academia and professionals of industry to exchange new ideas and application experiences in the highly active fields of micro-and nano-electronic circuits and integrated systems. It provided an excellent forum to present and discuss works on the emerging challenges offered by technology, in the areas of modeling, design, implementation and test of devices, circuits and systems.
At the conference A-IQ Ready partner Gonzalo Salinas from NVISION presented the project related PhD thesis and poster about SpeedEdge – Acceleration microarchitectures for Edge applications. The main goal of this PhD thesis is to develop novel acceleration solutions for AI and other state-of-the-art algorithms, addressing the technology gap in the transition of such workloads from the cloud to the edge. As a result, a flexible framework for acceleration of the fundamental operations of the AI algorithms, optimized to run on ultra-low-power IoT devices, will be proposed. This includes microarchitectural hardware modifications, software layer development, a mapping and optimization engine, the integration of the accelerators on a RISC-V SoC, and its final prototyping and evaluation on an FPGA. Keeping flexibility in mind, the platform developed in this PhD thesis will allow the execution of several AI workloads while optimizing performance and power consumption according to user or application requirements.
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